Software Trace Cache for Commercial Applications

Alex Ramirez, Josep Ll Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas

Research output: Contribution to journalArticle


In this paper we address the important problem of instruction fetch for future wide issue superscalar processors. Our approach focuses on understanding the interaction between software and hardware techniques targeting an increase in the instruction fetch bandwidth. That is the objective, for instance, of the Hardware Trace Cache (HTC). We design a profile based code reordering technique which targets a maximization of the sequentiality of instructions, while still trying to minimize instruction cache misses. We call our software approach, Software Trace Cache (STC). We evaluate our software approach, and then compare it with the HTC and the combination of both techniques. Our results on PostgreSQL show that for large codes with few loops and deterministic execution sequences the STC offers better results than a HTC. Also, both the software and hardware approaches combine well to obtain improved results.

Original languageEnglish (US)
Pages (from-to)373-395
Number of pages23
JournalInternational Journal of Parallel Programming
Issue number5
StatePublished - Oct 1 2002


  • Code layout
  • Instruction fetch
  • Software trace cache

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Information Systems

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