Virtual Instruction Set Computer (VISC) architectures define two separate instruction sets (one to serve as the representation of stored programs, and another to control the hardware), and use a hardware-specific translation layer to optimize and execute code on the hardware. This approach lends great flexibility to hardware and compiler design, enabling sophisticated hardware-specific optimizations at all stages of a program's lifetime. Building on our experience with the LLVM compiler infrastructure, we have proposed (1) a novel virtual instruction set for VISC architectures, and (2) a translation strategy that permits both offline and online translation, as well as dynamic optimization. Our V-ISA design is low-level and language-independent, yet retains enough high-level information to support sophisticated, "lifelong" optimization of software. The VISC strategy and V-ISA design also have important implications for high-level language virtual machines and for operating system kernels. We describe our instruction set design and translation strategy, and our ongoing work on dynamic optimization for VISC systems, and briefly discuss our work in the software implications of VISC systems.