SoftSig: Software-exposed hardware signatures for code analysis and optimization

James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas

Research output: Contribution to journalArticlepeer-review

Abstract

Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficiently and with low complexity with hardware signatures. To enable flexible use of signatures, this paper proposes to expose a Signature Register File to the software through a rich ISA. The software has great flexibility to decide, for each signature, which addresses to collect and which addresses to disambiguate against. We call this architecture SoftSig. In addition, as an example of SoftSig use, we show how to detect redundant function calls efficiently and eliminate them dynamically. We call this algorithm MemoiSE. On average for five popular applications, MemoiSE reduces the number of dynamic instructions by 9.3%, thereby reducing the execution time of the applications by 9%.

Original languageEnglish (US)
Pages (from-to)145-156
Number of pages12
JournalACM SIGPLAN Notices
Volume43
Issue number3
StatePublished - Mar 1 2008

Keywords

  • Memory Disambiguation
  • Multi-core Architectures
  • Runtime Optimization

ASJC Scopus subject areas

  • Computer Science(all)

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