SoftArch: An architecture-level tool for modeling and analyzing soft errors

Xiaodong Li, Sarita V Adve, Pradip Bose, Jude A. Rivers

Research output: Contribution to conferencePaper

Abstract

Soft errors are a growing concern for processor reliability Recent work has motivated architecture-level studies of soft errors since the architecture can mask many raw errors and architectural solutions can exploit workload knowledge. This paper proposes a model and tool, called SoftArch, to enable analysis of soft errors at the architecture-level in modern processors. SoftArch is based on a probabilistic model of the error generation and propagation process in a processor. Compared to prior architecture-level tools, SoftArch is more comprehensive or faster. We demonstrate the use of SoftArch for an out-of-order superscalar processor running SPEC2000 benchmarks. Our results are consistent with, but more comprehensive than, prior work, and motivate selective and dynamic architecture-level soft error protection mechanisms.

Original languageEnglish (US)
Pages496-505
Number of pages10
StatePublished - Nov 9 2005
Event2005 International Conference on Dependable Systems and Networks - Yokohama, Japan
Duration: Jun 28 2005Jul 1 2005

Other

Other2005 International Conference on Dependable Systems and Networks
CountryJapan
CityYokohama
Period6/28/057/1/05

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ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

Cite this

Li, X., Adve, S. V., Bose, P., & Rivers, J. A. (2005). SoftArch: An architecture-level tool for modeling and analyzing soft errors. 496-505. Paper presented at 2005 International Conference on Dependable Systems and Networks, Yokohama, Japan.