Soft-Failures Induced by System-Level ESD

Nicholas A. Thomson, Yang Xiu, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

Hundreds of static discharges were directed to a circuit board containing a custom test chip, and the resulting soft-failures were recorded. The large time-derivative of the ESD current is the primary cause of soft-failures in this system. Magnetic coupling between traces and bondwires produces glitches at IO pins; the magnitude of these glitches is increased by the bounce of the on-chip supply net relative to the on-board supply. Additionally, logic upsets due to substrate current collection are observed when the equipment-under-test is tethered, i.e., when it has a low impedance path to Earth-ground.

Original languageEnglish (US)
Article number7851026
Pages (from-to)90-98
Number of pages9
JournalIEEE Transactions on Device and Materials Reliability
Volume17
Issue number1
DOIs
StatePublished - Mar 2017

Keywords

  • IEC 61000-4-2
  • ISO 10605
  • System-level ESD
  • functionalfailure
  • soft-failure
  • substrate current

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

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