TY - JOUR
T1 - Soft-Error-Rate-Analysis (SERA) methodology
AU - Zhang, Ming
AU - Shanbhag, Naresh R.
N1 - Funding Information:
Manuscript received April 3, 2005; revised August 6, 2005. This work was supported by the Microelectronics Advanced Research Corporation (MARCO)-sponsored Gigascale Systems Research Center. This paper was recommended by Associate Editor C.-J. R. Shi.
PY - 2006/10
Y1 - 2006/10
N2 - We present a soft-error-rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis approach that employs a judicious mix of probability theory, circuit simulation, graph theory, and fault simulation. SERA achieves five orders of magnitude speedup over Monte Carlo-based simulation approaches with less than 5% error. Dependence of the soft-error rate (SER) of combinational logic circuits on a supply voltage, clock period, latching window, circuit topology, and input vector is explicitly captured and studied for a typical 0.18-μm CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an SER peaking phenomenon in multipliers is observed where the center bits have an SER that are orders of magnitude greater than those of the LSBs and the MSBs. An increase of up to 25% in the SER for multiplier circuits of various sizes has been observed as technology scales from 0.18 to 0.13 μm.
AB - We present a soft-error-rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis approach that employs a judicious mix of probability theory, circuit simulation, graph theory, and fault simulation. SERA achieves five orders of magnitude speedup over Monte Carlo-based simulation approaches with less than 5% error. Dependence of the soft-error rate (SER) of combinational logic circuits on a supply voltage, clock period, latching window, circuit topology, and input vector is explicitly captured and studied for a typical 0.18-μm CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an SER peaking phenomenon in multipliers is observed where the center bits have an SER that are orders of magnitude greater than those of the LSBs and the MSBs. An increase of up to 25% in the SER for multiplier circuits of various sizes has been observed as technology scales from 0.18 to 0.13 μm.
KW - Combinational logic circuits
KW - Integrated-circuit reliability
KW - Single-event transient (SET)
KW - Single-event upset (SEU)
KW - Soft error
KW - Soft-error rate (SER)
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U2 - 10.1109/TCAD.2005.862738
DO - 10.1109/TCAD.2005.862738
M3 - Article
AN - SCOPUS:33748331354
VL - 25
SP - 2140
EP - 2155
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 10
M1 - 1677697
ER -