Soft-Error-Rate-Analysis (SERA) methodology

Ming Zhang, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review

Abstract

We present a soft-error-rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis approach that employs a judicious mix of probability theory, circuit simulation, graph theory, and fault simulation. SERA achieves five orders of magnitude speedup over Monte Carlo-based simulation approaches with less than 5% error. Dependence of the soft-error rate (SER) of combinational logic circuits on a supply voltage, clock period, latching window, circuit topology, and input vector is explicitly captured and studied for a typical 0.18-μm CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an SER peaking phenomenon in multipliers is observed where the center bits have an SER that are orders of magnitude greater than those of the LSBs and the MSBs. An increase of up to 25% in the SER for multiplier circuits of various sizes has been observed as technology scales from 0.18 to 0.13 μm.

Original languageEnglish (US)
Article number1677697
Pages (from-to)2140-2155
Number of pages16
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume25
Issue number10
DOIs
StatePublished - Oct 2006

Keywords

  • Combinational logic circuits
  • Integrated-circuit reliability
  • Single-event transient (SET)
  • Single-event upset (SEU)
  • Soft error
  • Soft-error rate (SER)

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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