Single-VDD and Single-VT Super-Drowsy Techniques for Low-Leakage High-Performance Instruction Caches

Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor Mudge

Research output: Contribution to journalConference articlepeer-review

Abstract

In this paper, we present a circuit technique that supports a super-drowsy mode with a single-VDD. In addition, we perform a detailed working set analysis for various cache line update policies for placing lines in a drowsy state. The analysis presents a policy for an instruction cache and shows it is as good as or better than more complex schemes proposed in the past. Furthermore, as an alternative to using high-threshold devices to reduce the bitline leakage through access transistors in drowsy caches, we propose a gated bitline precharge technique. A single threshold process is now sufficient. The gated precharge employs a simple but effective predictor that almost completely hides any performance loss incurred by the transitions between sub-banks. A 64-entry predictor with 3 bits per entry reduces the run-time increase by 78%, which is as effective as previous proposals that used content addressable predictors with 40 bits per entry. Overall, the combination of the proposed techniques reduces the leakage power by 72% with negligible (0.4%) run-time increase.

Original languageEnglish (US)
Article number1349307
Pages (from-to)54-57
Number of pages4
JournalProceedings of the International Symposium on Low Power Electronics and Design
Volume2004-January
Issue numberJanuary
DOIs
StatePublished - Jan 1 2004
Externally publishedYes
Event2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States
Duration: Aug 9 2004Aug 11 2004

Keywords

  • Leakage current
  • Low power

ASJC Scopus subject areas

  • Engineering(all)

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