Simultaneous routing and buffer insertion with restrictions on buffer locations

Hai Zhou; D. F. Wong; I. Min Liu; Adnan Aziz

doi:10.1109/43.851998

Simultaneous routing and buffer insertion with restrictions on buffer locations

Hai Zhou, D. F. Wong, I. Min Liu, Adnan Aziz

Research output: Contribution to journal › Article › peer-review

Abstract

During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay.

Original language	English (US)
Pages (from-to)	819-824
Number of pages	6
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	19
Issue number	7
DOIs	https://doi.org/10.1109/43.851998
State	Published - Jul 1 2000
Externally published	Yes

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/43.851998

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Simultaneous routing and buffer insertion with restrictions on buffer locations

Abstract

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