Simultaneous escape-routing algorithms for via minimization of high-speed boards

Muhammet Mustafa Ozdal, Martin D.F. Wong, Philip S. Honsinger

Research output: Contribution to journalArticlepeer-review


Shrinking transistor sizes, increasing circuit complexities, and high clock frequencies bring new board-routing challenges that cannot be handled effectively by traditional routing algorithms. Many high-end designs in the industry today require manual routing efforts, which increases the design-cycle times considerably. In this paper, we propose an escape-routing algorithm to route nets within multiple dense components simultaneously so that the number of crossings in the intermediate area is minimized. We also show how to handle high-speed-design constraints within the framework of this algorithm. Experimental comparisons with a recently proposed algorithm show that our algorithm reduces the via requirements of industrial test cases on average by 39%.

Original languageEnglish (US)
Pages (from-to)84-94
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number1
StatePublished - Jan 2008


  • Design constraints
  • Escape routing
  • Package routing
  • Printed circuit board
  • Randomized algorithms
  • Via minimization

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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