Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation

Sopan Joshi; Elyse Rosenbaum

doi:10.1016/S0026-2714(03)00130-6

Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation

Research output: Contribution to journal › Article › peer-review

Abstract

We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.

Original language	English (US)
Pages (from-to)	1021-1027
Number of pages	7
Journal	Microelectronics Reliability
Volume	43
Issue number	7
DOIs	https://doi.org/10.1016/S0026-2714(03)00130-6
State	Published - Jul 2003

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Safety, Risk, Reliability and Quality
Surfaces, Coatings and Films
Atomic and Molecular Physics, and Optics
Electrical and Electronic Engineering

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10.1016/S0026-2714(03)00130-6

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title = "Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation",

abstract = "We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.",

author = "Sopan Joshi and Elyse Rosenbaum",

note = "Funding Information: This work was funded by the Semiconductor Research Corporation, Research ID 955. R. Ida, Motorola, is thanked for providing test devices and donating the vector network analyzer. G. Kaatz, Motorola, is thanked for steering us in this research direction. S. Joshi gratefully acknowledges useful conversations with C.C. McAndrew, Motorola, and J. Li, UIUC. E. Rosenbaum thanks G. Groeseneken and H. Maes, IMEC, for providing her with facilities for the initial device characterization. The authors acknowledge T. Smedes, Philips, C. Russ, Sarnoff, and H. Gieser, Fraunhofer, for their mentoring of this paper. ",

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month = jul,

doi = "10.1016/S0026-2714(03)00130-6",

language = "English (US)",

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AU - Rosenbaum, Elyse

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N2 - We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.

AB - We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.

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Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation

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