Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation

Sopan Joshi, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.

Original languageEnglish (US)
Pages (from-to)1021-1027
Number of pages7
JournalMicroelectronics Reliability
Volume43
Issue number7
DOIs
StatePublished - Jul 1 2003

Fingerprint

Circuit simulation
simulators
Transistors
transistors
Simulators
Silicon
high current
simulation
breakdown
impedance
inclusions
silicon

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Safety, Risk, Reliability and Quality
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation. / Joshi, Sopan; Rosenbaum, Elyse.

In: Microelectronics Reliability, Vol. 43, No. 7, 01.07.2003, p. 1021-1027.

Research output: Contribution to journalArticle

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