Abstract
We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.
Original language | English (US) |
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Pages (from-to) | 1021-1027 |
Number of pages | 7 |
Journal | Microelectronics Reliability |
Volume | 43 |
Issue number | 7 |
DOIs | |
State | Published - Jul 2003 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Safety, Risk, Reliability and Quality
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering