An approach to electrical analysis of VLSI packaging interconnections using computer simulation is discussed. Corresponding simulation software developed during the course of research on VLSI interconnections is described. Examples of application to prototypical interconnections (two-transmission-line systems joined by a lumped-parameter network and a transmission line terminated by a network of bipolar and MOS transistors) are provided. Simulation results for the above examples are presented and analyzed. The current status of work is discussed, and directions of future research are delineated.
|Original language||English (US)|
|Number of pages||6|
|Journal||Proceedings - Electronic Components and Technology Conference|
|State||Published - Dec 1 1989|
ASJC Scopus subject areas
- Electrical and Electronic Engineering