Simulation of Transients in VLSI Packaging Interconnections

Olgierd A. Palusinski; J. C. Liao; John L. Prince; Andreas C. Cangellaris

doi:10.1109/33.52865

Simulation of Transients in VLSI Packaging Interconnections

Olgierd A. Palusinski, J. C. Liao, John L. Prince, Andreas C. Cangellaris

Research output: Contribution to journal › Article › peer-review

Abstract

An approach to electrical analysis of VLSI packaging interconnections via computer simulation is presented. Corresponding simulation software developed during the course of research on VLSI interconnections conducted at the University of Arizona is also described. Examples of application to prototypical interconnections (two transmission line systems joined by a lumped parameter network and a transmission line terminated by a network of bipolar and MOS transistors) are provided. The results of simulation of the above examples are presented and analyzed. Discussion of current status of work is also included and directions of future research delineated.

Original language	English (US)
Pages (from-to)	160-166
Number of pages	7
Journal	IEEE Transactions on Components, Hybrids, and Manufacturing Technology
Volume	13
Issue number	1
DOIs	https://doi.org/10.1109/33.52865
State	Published - Mar 1990
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
General Engineering
Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

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10.1109/33.52865

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title = "Simulation of Transients in VLSI Packaging Interconnections",

abstract = "An approach to electrical analysis of VLSI packaging interconnections via computer simulation is presented. Corresponding simulation software developed during the course of research on VLSI interconnections conducted at the University of Arizona is also described. Examples of application to prototypical interconnections (two transmission line systems joined by a lumped parameter network and a transmission line terminated by a network of bipolar and MOS transistors) are provided. The results of simulation of the above examples are presented and analyzed. Discussion of current status of work is also included and directions of future research delineated.",

author = "Palusinski, {Olgierd A.} and Liao, {J. C.} and Prince, {John L.} and Cangellaris, {Andreas C.}",

note = "Funding Information: Manuscript received March 1, 1989; revised September 15, 1989. This research was supported in part by Semiconductor Research Corporation under Contracts 84-06-050, 86-07-086, and 87-MP-086. This paper was presented at the 39th Electronic Components Conference, Houston, TX, May 22-24, 1989. The authors are with the Department of Electrical and Computer Engineering, The University of Arizona, Tucson, AZ 85721. IEEE Log Number 8933189.",

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AU - Palusinski, Olgierd A.

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AU - Prince, John L.

AU - Cangellaris, Andreas C.

N1 - Funding Information: Manuscript received March 1, 1989; revised September 15, 1989. This research was supported in part by Semiconductor Research Corporation under Contracts 84-06-050, 86-07-086, and 87-MP-086. This paper was presented at the 39th Electronic Components Conference, Houston, TX, May 22-24, 1989. The authors are with the Department of Electrical and Computer Engineering, The University of Arizona, Tucson, AZ 85721. IEEE Log Number 8933189.

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Simulation of Transients in VLSI Packaging Interconnections

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