Simulated Fault Injection: A Methodology to Evaluate Fault Tolerant Microprocessor Architectures

Gwan S. Choi, Ravishankar K. Iyer, Victor A. Carreno

Research output: Contribution to journalArticlepeer-review

Abstract

This paper describes a simulation-based fault injection methodology to validate fault tolerant microprocessor architectures. The approach uses mixed-mode simulation (electrical/logic analysis), and injects transient errors in run-time, to assess the resulting fault-impact. To exemplify the methodology, a fault tolerant architecture which models the digital aspects of a dual channel, real-time jet engine controller is used. The level of effectiveness of the dual configuration to single and multiple transients is measured. The results indicate 100% coverage of single transients. Approximately 12 percent of the multiple transients affect both channels; none result in controller failure since two additional levels of redundancy exist.

Original languageEnglish (US)
Pages (from-to)486-491
Number of pages6
JournalIEEE Transactions on Reliability
Volume39
Issue number4
DOIs
StatePublished - Oct 1990

Keywords

  • Experimental analysis
  • Fault injection
  • Fault-tolerance
  • Simulation
  • Validation

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

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