Abstract
This paper describes a simulation-based fault injection methodology to validate fault tolerant microprocessor architectures. The approach uses mixed-mode simulation (electrical/logic analysis), and injects transient errors in run-time, to assess the resulting fault-impact. To exemplify the methodology, a fault tolerant architecture which models the digital aspects of a dual channel, real-time jet engine controller is used. The level of effectiveness of the dual configuration to single and multiple transients is measured. The results indicate 100% coverage of single transients. Approximately 12 percent of the multiple transients affect both channels; none result in controller failure since two additional levels of redundancy exist.
Original language | English (US) |
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Pages (from-to) | 486-491 |
Number of pages | 6 |
Journal | IEEE Transactions on Reliability |
Volume | 39 |
Issue number | 4 |
DOIs | |
State | Published - Oct 1990 |
Keywords
- Experimental analysis
- Fault injection
- Fault-tolerance
- Simulation
- Validation
ASJC Scopus subject areas
- Safety, Risk, Reliability and Quality
- Electrical and Electronic Engineering