This paper presents a non-lithographic approach to generate wafer-scale single crystal silicon nanowires (SiNWs) with controlled sidewall profile and surface morphology. The approach begins with silver (Ag) thin-film thermal dewetting, gold (Au) deposition and lift-off to generate a large-scale Au mesh on Si substrates. This is followed by metal-assisted chemical etching (MacEtch), where the Au mesh serves as a catalyst to produce arrays of smooth Si nanowires with tunable taper up to 13°. The mean diameter of the thus fabricated SiNWs can be controlled to range from 62 to 300 nm with standard deviations as small as 13.6 nm, and the areal coverage of the wire arrays can be up to 46%. Control of the mean wire diameter is achieved by controlling the pore diameter of the metallic mesh which is, in turn, controlled by adjusting the initial thin-film thickness and deposition rate. To control the wire surface morphology, a post-fabrication roughening step is added to the approach. This step uses Au nanoparticles and slow-rate MacEtch to produce rms surface roughness up to 3.6 nm.
ASJC Scopus subject areas
- Materials Science(all)
- Mechanics of Materials
- Mechanical Engineering
- Electrical and Electronic Engineering