Signature analyzer design for yield learning support

Nishant P. Patil, Subhasish Mitra, Steven S. Lumetta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Signature analyzers are designed to enable identification of failing test response bits directly from failing signatures, without any special diagnosis mode. This ability is useful for yield learning from the large volume of data available from failing chips during production lest. The signature analyzers described also tolerate unknown logic values (X's) and are useful for Built-In-Self-Test and test compression with yield analysis support. Actual defective chip data demonstrates the effectiveness of the presented techniques. Depending on the desired accuracy of failing response bit identification and the number of X's, test response data is reduced by up to two orders of magnitude.

Original languageEnglish (US)
Title of host publication2006 IEEE International Test Conference, ITC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)1424402921, 9781424402922
DOIs
StatePublished - Jan 1 2006
Event2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: Oct 22 2006Oct 27 2006

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Other

Other2006 IEEE International Test Conference, ITC
CountryUnited States
CitySanta Clara, CA
Period10/22/0610/27/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

Fingerprint Dive into the research topics of 'Signature analyzer design for yield learning support'. Together they form a unique fingerprint.

Cite this