Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures

Charbel Sakr, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review


This paper presents signal processing methods to enhance the energy vs. accuracy trade-off of in-memory computing (IMC) architectures. First, an optimal clipping criterion (OCC) for signal quantization is proposed in order to minimize the precision of column analog-to-digital converters (ADCs) at iso-accuracy. For a Gaussian distributed signal, the OCC is shown to reduce the column ADC precision requirements by 3 bits at a signal-to-quantization noise ratio (SQNR) of 22.5}\dB over the commonly used full range (FR) quantizer. Next, the input-sliced weight-parallel (ISWP) IMC architecture is presented as a generalization of the popular bit-serial bit-parallel (BSBP) architecture. Quantization noise analysis of the ISWP indicates that its accuracy is comparable to BSBP while providing an order-of-magnitude reduction in energy consumption due to fewer array invocations and smaller ADC precision. Combining OCC and ISWP noise analysis, we map popular DNNs such as VGG-9 (CIFAR-10), ResNet-18 (CIFAR-10), and AlexNet (ImageNet) on a OCC-enabled ISWP architecture and show a reduction in energy consumption by an order-of-magnitude at iso-accuracy over the BSBP architecture that employs FR-based ADCs.

Original languageEnglish (US)
Pages (from-to)6462-6472
Number of pages11
JournalIEEE Transactions on Signal Processing
StatePublished - 2021


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  • Optimal clipping
  • in-memory computing
  • bit slicing
  • quantization

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering


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