Abstract
This paper presents signal processing methods to enhance the energy vs. accuracy trade-off of in-memory computing (IMC) architectures. First, an optimal clipping criterion (OCC) for signal quantization is proposed in order to minimize the precision of column analog-to-digital converters (ADCs) at iso-accuracy. For a Gaussian distributed signal, the OCC is shown to reduce the column ADC precision requirements by 3 bits at a signal-to-quantization noise ratio (SQNR) of 22.5}\dB over the commonly used full range (FR) quantizer. Next, the input-sliced weight-parallel (ISWP) IMC architecture is presented as a generalization of the popular bit-serial bit-parallel (BSBP) architecture. Quantization noise analysis of the ISWP indicates that its accuracy is comparable to BSBP while providing an order-of-magnitude reduction in energy consumption due to fewer array invocations and smaller ADC precision. Combining OCC and ISWP noise analysis, we map popular DNNs such as VGG-9 (CIFAR-10), ResNet-18 (CIFAR-10), and AlexNet (ImageNet) on a OCC-enabled ISWP architecture and show a reduction in energy consumption by an order-of-magnitude at iso-accuracy over the BSBP architecture that employs FR-based ADCs.
Original language | English (US) |
---|---|
Pages (from-to) | 6462-6472 |
Number of pages | 11 |
Journal | IEEE Transactions on Signal Processing |
Volume | 69 |
DOIs | |
State | Published - 2021 |
Keywords
- Class
- Conferences
- IEEEtran
- Indexes
- L A T E X
- Licenses
- Loading
- Portable document format
- Printing
- Typesetting
- paper
- style
- template
- typesetting
- Optimal clipping
- in-memory computing
- bit slicing
- quantization
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering