Sign-Off Timing Considerations via Concurrent Routing Topology Optimization

Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin Wong

Research output: Contribution to journalArticlepeer-review

Abstract

Timing closure is considered across the circuit design flow. Generally, the early-stage timing optimization can only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or pre-routing path length, since obtaining sign-off performance needs a time-consuming routing flow. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. Therefore, we utilize the power of deep learning techniques to bridge the gap between the early-stage analysis and the sign-off analysis. A well-designed deep learning framework guides the adjustment of Steiner points to enable explicit early-stage timing optimization. Cooperating with deep Steiner point adjustment, we propose the routing topology reconstruction to accelerate the convergence and hold a reasonable routing topology. Further, we also introduce Steiner point simplification as a post-processing technique to avoid unnecessary routing constraints. This paper demonstrates the ability of the learning-Assist framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs. With Steiner point adjustment alone, TSteinerPt, can help the SOTA open-source router to obtain 11.2% and 7.1% improvement for the sign-off worst negative slack and total negative slack, respectively. Under the additional joint optimization with routing topology reconstruction and simplification, TSteinerRec can further save 25.9% optimization duration with a better sign-off performance.

Original languageEnglish (US)
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOIs
StateAccepted/In press - 2024
Externally publishedYes

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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