TY - JOUR
T1 - Sign-Off Timing Considerations via Concurrent Routing Topology Optimization
AU - Liu, Siting
AU - Wang, Ziyi
AU - Liu, Fangzhou
AU - Lin, Yibo
AU - Yu, Bei
AU - Wong, Martin
N1 - This work is supported in part by The Research Grants Council of Hong Kong SAR (Project No. CUHK14211824) and the MIND project (MINDXZ202404). Siting Liu, Ziyi Wang, Fangzhou Liu and Bei Yu are with the Department of Computer Science and Engineering, The Chinese University of Hong Kong, NT, Hong Kong SAR. Yibo Lin is with School of Integrated Circuits, Peking University, China. Martin Wong is with Hong Kong Baptist University, Hong Kong SAR.
PY - 2024
Y1 - 2024
N2 - Timing closure is considered across the circuit design flow. Generally, the early-stage timing optimization can only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or pre-routing path length, since obtaining sign-off performance needs a time-consuming routing flow. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. Therefore, we utilize the power of deep learning techniques to bridge the gap between the early-stage analysis and the sign-off analysis. A well-designed deep learning framework guides the adjustment of Steiner points to enable explicit early-stage timing optimization. Cooperating with deep Steiner point adjustment, we propose the routing topology reconstruction to accelerate the convergence and hold a reasonable routing topology. Further, we also introduce Steiner point simplification as a post-processing technique to avoid unnecessary routing constraints. This paper demonstrates the ability of the learning-Assist framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs. With Steiner point adjustment alone, TSteinerPt, can help the SOTA open-source router to obtain 11.2% and 7.1% improvement for the sign-off worst negative slack and total negative slack, respectively. Under the additional joint optimization with routing topology reconstruction and simplification, TSteinerRec can further save 25.9% optimization duration with a better sign-off performance.
AB - Timing closure is considered across the circuit design flow. Generally, the early-stage timing optimization can only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or pre-routing path length, since obtaining sign-off performance needs a time-consuming routing flow. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. Therefore, we utilize the power of deep learning techniques to bridge the gap between the early-stage analysis and the sign-off analysis. A well-designed deep learning framework guides the adjustment of Steiner points to enable explicit early-stage timing optimization. Cooperating with deep Steiner point adjustment, we propose the routing topology reconstruction to accelerate the convergence and hold a reasonable routing topology. Further, we also introduce Steiner point simplification as a post-processing technique to avoid unnecessary routing constraints. This paper demonstrates the ability of the learning-Assist framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs. With Steiner point adjustment alone, TSteinerPt, can help the SOTA open-source router to obtain 11.2% and 7.1% improvement for the sign-off worst negative slack and total negative slack, respectively. Under the additional joint optimization with routing topology reconstruction and simplification, TSteinerRec can further save 25.9% optimization duration with a better sign-off performance.
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U2 - 10.1109/TCAD.2024.3506216
DO - 10.1109/TCAD.2024.3506216
M3 - Article
AN - SCOPUS:85210967858
SN - 0278-0070
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ER -