Short-channel enhancement-mode planar GaAs nanowire HEMTs through a bottom-up method

Miao Xin, Zhang Chen, Xiuling Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Bottom-up self-assembled planar nanowires (NWs) are of great interest for device application because they can be readily integrated using conventional processing technique. Planar GaAs NWs have been demonstrated to have great crystal quality (free from top-down dry etching damages) and high electron mobility. Considering NWs' 3D geometry, planar NW-FETs inherently benefit from the enhanced electron confinement and electrostatic gate control which are essential to suppress short channel effects and enable the down-scaling of modern transistors. We had fabricated multiple channel planar NW high electron mobility transistors (NW-HEMTs) with self-aligned intrinsic planar <60;110> GaAs NWs capped with Si doped Al xGa 1-xAs thin film as the channel on semi-insulating (100) GaAs substrates and demonstrated the feasibility of wafer-scale electrical uniformity of bottom-up NW-FETs previously [1-4]. However, these prototype multiple channel planar NW-HEMTs were of 1.2μm gate length and ∼250nm NW diameter in the channel.

Original languageEnglish (US)
Title of host publication70th Device Research Conference, DRC 2012 - Conference Digest
Number of pages2
StatePublished - Oct 5 2012
Event70th Device Research Conference, DRC 2012 - University Park, PA, United States
Duration: Jun 18 2012Jun 20 2012

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770


Other70th Device Research Conference, DRC 2012
Country/TerritoryUnited States
CityUniversity Park, PA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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