Sharing-aware mapping and parallel architectures

Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux

Research output: Chapter in Book/Report/Conference proceedingChapter


The difference in the memory locality between the cores affects the data sharing performance. As parallel applications need to access shared data, a complex memory hierarchy presents challenges for mapping threads to cores, and data to NUMA nodes (Wang et al., Performance analysis of thread mappings with a holistic view of the hardware resources. In: IEEE International symposium on performance analysis of systems & software (ISPASS), 2012). Threads that access a large amount of shared data should be mapped to cores that are close to each other in the memory hierarchy, while data should be mapped to the NUMA node executing the threads that access them (Ribeiro et al., Memory affinity for hierarchical shared memory multiprocessors. In: International symposium on computer architecture and high performance computing (SBAC-PAD), pp 59–66, 2009). In this way, the locality of the memory accesses is improved, which leads to an increase of performance and energy efficiency. For optimal performance improvements, data and thread mapping should be performed together (Terboven et al., Data and thread affinity in OpenMP programs. In: Workshop on memory access on future processors: a solved problem? (MAW), pp 377–384, 2008).

Original languageEnglish (US)
Title of host publicationSpringerBriefs in Computer Science
PublisherSpringer Nature
Number of pages9
StatePublished - 2018

Publication series

NameSpringerBriefs in Computer Science
ISSN (Print)2191-5768
ISSN (Electronic)2191-5776

ASJC Scopus subject areas

  • Computer Science(all)


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