Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance

Youxin Gao, D. F. Wong

Research output: Contribution to journalArticlepeer-review


In this paper, by using calculus of variations, we determine the optimal shape for a wire under the Elmore delay model. Coupling capacitance has been taken into consideration explicitly by treating it as another source of grounded capacitance. Given two wires in parallel, one has uniform width and the other has non-uniform width whose shape is described by a function f(x). Let TD be the delay through the non-uniform wire. We determine f(x) such that TD is minimized. We also extend our study to the case where a non-uniform wire has two neighboring wires. Our study shows that the optimal shape function satisfies an integral equation. Numerical methods are employed to solve the corresponding differential equation and carry out the integration. We provide an efficient algorithm to find the optimal solution. Experiments show that it only takes several iterations to get the optimal results by using our algorithm. Our experiments also show that the wire delay TD is a convex function of the wire width at the driver end.

Original languageEnglish (US)
Pages (from-to)165-178
Number of pages14
JournalIntegration, the VLSI Journal
Issue number2
StatePublished - Jul 1999
Externally publishedYes

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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