Sequential equivalence checking between system level and RTL descriptions

Keyphrases

• System Level 100%
• Level Description 100%
• Register Transfer Level 100%
• Sequential Equivalence Checking 100%
• Equivalence Checking 100%
• Symbolic Expression 66%
• Design Description 66%
• System-on-chip 33%
• Hardware Description Language 33%
• Sequential Behavior 33%
• SAT Solver 33%
• Viterbi Decoder 33%
• Verilog 33%
• Design Behaviour 33%
• Functional Mapping 33%
• Language Description 33%

Computer Science

• Level Description 100%
• Register-Transfer Level 100%
• Equivalence Checking 100%
• Register-Transfer-Level Implementation 50%
• Symbolic Expression 50%
• Case Study 25%
• Checking Technique 25%
• System on a Chip 25%
• Verilog 25%
• Hardware Description Languages 25%