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Sequential element design with built-in soft error resilience
Ming Zhang
, Subhasish Mitra
, T. M. Mak
, Norbert Seifert
, Nicholas J. Wang
, Quan Shi
, Kee Sup Kim
,
Naresh R. Shanbhag
,
Sanjay J. Patel
Electrical and Computer Engineering
Information Trust Institute
Coordinated Science Lab
European Union Center
Office of the Provost and Executive Vice Chancellor
Siebel School of Computing and Data Science
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peer-review
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Keyphrases
Element Design
100%
Sequential Elements
100%
Soft Error Resilience
100%
Soft Error Rate
100%
Flip-flop
75%
Chip-level
75%
Flip-flop Design
50%
Error-correcting
50%
Circuit Simulation
25%
On chip
25%
Error Correction Mechanism
25%
Cellular Level
25%
Multiple Applications
25%
Power Efficient
25%
Selective Placement
25%
Improvement Factor
25%
Scan Design
25%
Fault Injection
25%
Reliability Constraint
25%
Area Overhead
25%
Soft Error
25%
Minimal Speed
25%
Microprocessor Model
25%
Design for Testability
25%
Radiation-induced Soft Errors
25%
Design Debugging
25%
Error-correcting Codes
25%
90-nm CMOS Technology
25%
Increased Power
25%
Engineering
Design for testability
10%