TY - JOUR
T1 - Sequential element design with built-in soft error resilience
AU - Zhang, Ming
AU - Mitra, Subhasish
AU - Mak, T. M.
AU - Seifert, Norbert
AU - Wang, Nicholas J.
AU - Shi, Quan
AU - Kim, Kee Sup
AU - Shanbhag, Naresh R.
AU - Patel, Sanjay J.
N1 - Manuscript received August 30, 2005. This work was supported in part by MARCO Gigascale Systems Research Center (GSRC). M. Zhang, T. M. Mak, N. Seifert, Q. Shi, and K. S. Kim are with Intel Corporation, Folsom, CA 95630 USA (e-mail: [email protected]). S. Mitra is with the Department of Electrical Engineering, Stanford University, Stanford, CA 94305 USA. N. J. Wang, N. R. Shanbhag, and S. J. Patel are with the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. Digital Object Identifier 10.1109/TVLSI.2006.887832
PY - 2006/12
Y1 - 2006/12
N2 - This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements.
AB - This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements.
KW - Circuit simulation
KW - Error correction
KW - Fault injection
KW - Sequential element design
KW - Soft error rate (SER)
UR - http://www.scopus.com/inward/record.url?scp=33846595665&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33846595665&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2006.887832
DO - 10.1109/TVLSI.2006.887832
M3 - Article
AN - SCOPUS:33846595665
SN - 1063-8210
VL - 14
SP - 1368
EP - 1376
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 12
ER -