Sensor network-on-chip

Girish V. Varatkar; Sriram Narayanan; Naresh R Shanbhag; Douglas L Jones

doi:10.1109/ISSOC.2007.4427447

Sensor network-on-chip

Girish V. Varatkar, Sriram Narayanan, Naresh R Shanbhag, Douglas L Jones

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC), In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed to recover the performance of the system in the presence of errors especially timing errors, We apply this framework to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Simulations in IBM's 130nm CMOS process technology demonstrate up to 36% power savings compared to the conventional architecture for a detection probability of P_D = 0.5.

Original language	English (US)
Title of host publication	2007 International Symposium on System-on-Chip Proceedings, SOC
DOIs	https://doi.org/10.1109/ISSOC.2007.4427447
State	Published - Dec 1 2007
Event	2007 International Symposium on System-on-Chip, SOC - Tampere, Finland Duration: Nov 20 2007 → Nov 21 2007

Publication series

Name	2007 International Symposium on System-on-Chip Proceedings, SOC

Other

Other	2007 International Symposium on System-on-Chip, SOC
Country	Finland
City	Tampere
Period	11/20/07 → 11/21/07

ASJC Scopus subject areas

Control and Systems Engineering
Electrical and Electronic Engineering

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title = "Sensor network-on-chip",

abstract = "In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC), In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed to recover the performance of the system in the presence of errors especially timing errors, We apply this framework to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Simulations in IBM's 130nm CMOS process technology demonstrate up to 36% power savings compared to the conventional architecture for a detection probability of PD = 0.5.",

author = "Varatkar, {Girish V.} and Sriram Narayanan and Shanbhag, {Naresh R} and Jones, {Douglas L}",

year = "2007",

month = dec,

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doi = "10.1109/ISSOC.2007.4427447",

language = "English (US)",

isbn = "1424413672",

series = "2007 International Symposium on System-on-Chip Proceedings, SOC",

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AU - Varatkar, Girish V.

AU - Narayanan, Sriram

AU - Shanbhag, Naresh R

AU - Jones, Douglas L

PY - 2007/12/1

Y1 - 2007/12/1

N2 - In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC), In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed to recover the performance of the system in the presence of errors especially timing errors, We apply this framework to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Simulations in IBM's 130nm CMOS process technology demonstrate up to 36% power savings compared to the conventional architecture for a detection probability of PD = 0.5.

AB - In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC), In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed to recover the performance of the system in the presence of errors especially timing errors, We apply this framework to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Simulations in IBM's 130nm CMOS process technology demonstrate up to 36% power savings compared to the conventional architecture for a detection probability of PD = 0.5.

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DO - 10.1109/ISSOC.2007.4427447

M3 - Conference contribution

AN - SCOPUS:48149087451

SN - 1424413672

SN - 9781424413676

T3 - 2007 International Symposium on System-on-Chip Proceedings, SOC

BT - 2007 International Symposium on System-on-Chip Proceedings, SOC

T2 - 2007 International Symposium on System-on-Chip, SOC

Y2 - 20 November 2007 through 21 November 2007

ER -

Sensor network-on-chip

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