Sensor network-on-chip

Girish V. Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas Jones

Research output: Chapter in Book/Report/Conference proceedingConference contribution


In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC), In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed to recover the performance of the system in the presence of errors especially timing errors, We apply this framework to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Simulations in IBM's 130nm CMOS process technology demonstrate up to 36% power savings compared to the conventional architecture for a detection probability of PD = 0.5.

Original languageEnglish (US)
Title of host publication2007 International Symposium on System-on-Chip Proceedings, SOC
StatePublished - 2007
Event2007 International Symposium on System-on-Chip, SOC - Tampere, Finland
Duration: Nov 20 2007Nov 21 2007

Publication series

Name2007 International Symposium on System-on-Chip Proceedings, SOC


Other2007 International Symposium on System-on-Chip, SOC

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering


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