TY - GEN
T1 - Sensor network-on-chip
AU - Varatkar, Girish V.
AU - Narayanan, Sriram
AU - Shanbhag, Naresh R
AU - Jones, Douglas L
PY - 2007/12/1
Y1 - 2007/12/1
N2 - In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC), In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed to recover the performance of the system in the presence of errors especially timing errors, We apply this framework to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Simulations in IBM's 130nm CMOS process technology demonstrate up to 36% power savings compared to the conventional architecture for a detection probability of PD = 0.5.
AB - In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC), In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed to recover the performance of the system in the presence of errors especially timing errors, We apply this framework to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Simulations in IBM's 130nm CMOS process technology demonstrate up to 36% power savings compared to the conventional architecture for a detection probability of PD = 0.5.
UR - http://www.scopus.com/inward/record.url?scp=48149087451&partnerID=8YFLogxK
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U2 - 10.1109/ISSOC.2007.4427447
DO - 10.1109/ISSOC.2007.4427447
M3 - Conference contribution
AN - SCOPUS:48149087451
SN - 1424413672
SN - 9781424413676
T3 - 2007 International Symposium on System-on-Chip Proceedings, SOC
BT - 2007 International Symposium on System-on-Chip Proceedings, SOC
T2 - 2007 International Symposium on System-on-Chip, SOC
Y2 - 20 November 2007 through 21 November 2007
ER -