Semiconductor devices and methods are disclosed in which the amount of p-type material can be minimized, with attendant advantages in electrical, thermal, and optical performance, and in fabrication. A form of the disclosure is directed to a generally planar semiconductor device wherein a layer of p-type semiconductor material is disposed over a layer of n-type semiconductor material, and an electric potential is coupled between the p-type layer and the n-type layer, and wherein current in the device that is lateral to the plane of the layers is coupled into the p-type layer. A tunnel junction is adjacent the p-type layer for converting the lateral current into hole current. In an embodiment of this form of the disclosure, the tunnel junction is an n+/p+ junction oriented with the p+ portion thereof adjacent the p-type layer. The lateral current can be electron current in the n+ layer and/or electron current in a further layer of n-type material disposed over the tunnel junction.
|Original language||English (US)|
|U.S. patent number||5936266|
|State||Published - Aug 10 1999|