Semi-Coherent DMA: An Alternative I/O Coherency Management for Embedded Systems

Seungwon Min, Mohammad Alian, Wen Mei Hwu, Nam Sung Kim

Research output: Contribution to journalArticle

Abstract

Many modern embedded CPUs adopt Non-Coherent DMA (NC-DMA) over Coherent DMA (C-DMA) because of simplicity. An NC-DMA design, however, requires a CPU device driver to explicitly invalidate or flush a wide range of cache space. When an I/O DMA device writes data to a main memory region, the CPU needs to invalidate the cache space corresponding to the same memory region twice: (1) to prevent dirty cache lines from overwriting the DMA data and (2) to remove any cache lines prefetched before the DMA is done. In this work, we first show that such explicit invalidations consume 31 percent of CPU cycles, limiting the data transfer throughput of a high-speed network interface card (NIC) when receiving network packets. Second, we propose a Semi-Coherent DMA (SC-DMA) architecture for improving the efficiency of NC-DMA with a slight modification to the hardware. Specifically, our SC-DMA records the DMA region and prohibits any data that is prefetched from the region from entering the cache, reducing nearly 50 percent of the unnecessary invalidations. Lastly, we identify several software optimizations that can substantially reduce excessive cache invalidations prevalent in NIC drivers. Our evaluation with NVIDIA Jetson TX2 shows that our proposed SC-DMA design with the NIC driver optimizations can improve the NIC data transfer throughput by up to 53.3 percent.

Original languageEnglish (US)
Article number8444757
Pages (from-to)221-224
Number of pages4
JournalIEEE Computer Architecture Letters
Volume17
Issue number2
DOIs
StatePublished - Jul 1 2018

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Keywords

  • 'E'thernet
  • Cache
  • Internet of Things
  • embedded processor

ASJC Scopus subject areas

  • Hardware and Architecture

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