Secure hierarchy-aware cache replacement policy (SHARP): Defending against cache-based side channel atacks

Mengjia Yan, Bhargava Gopireddy, Thomas Shull, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In cache-based side channel attacks, a spy that shares a cache with a victim probes cache locations to extract information on the victim's access patterns. For example, in evict+reload, the spy repeatedly evicts and then reloads a probe address, checking if the victim has accessed the address in between the two operations. While there are many proposals to combat these cache attacks, they all have limitations: they either hurt performance, require programmer intervention, or can only defend against some types of attacks. This paper makes the following observation for an environment with an inclusive cache hierarchy: when the spy evicts the probe address from the shared cache, the address will also be evicted from the private cache of the victim process, creating an inclusion victim. Consequently, to disable cache attacks, this paper proposes to alter the line replacement algorithm of the shared cache, to prevent a process from creating inclusion victims in the caches of cores running other processes. By enforcing this rule, the spy cannot evict the probe address from the shared cache and, hence, cannot glimpse any information on the victim's access patterns. We call our proposal SHARP (Secure Hierarchy-Aware cache Replacement Policy). SHARP effciently defends against all existing cross-core shared-cache attacks, needs only minimal hardware modifcations, and requires no code modifcations. We implement SHARP in a cycle-level full-system simulator. We show that it protects against real-world attacks, and that it introduces negligible average performance degradation.

Original languageEnglish (US)
Title of host publicationISCA 2017 - 44th Annual International Symposium on Computer Architecture - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages347-360
Number of pages14
ISBN (Electronic)9781450348928
DOIs
StatePublished - Jun 24 2017
Event44th Annual International Symposium on Computer Architecture - ISCA 2017 - Toronto, Canada
Duration: Jun 24 2017Jun 28 2017

Publication series

NameProceedings - International Symposium on Computer Architecture
VolumePart F128643
ISSN (Print)1063-6897

Other

Other44th Annual International Symposium on Computer Architecture - ISCA 2017
Country/TerritoryCanada
CityToronto
Period6/24/176/28/17

Keywords

  • Cache
  • Cache replacement
  • Security
  • Side channel

ASJC Scopus subject areas

  • Hardware and Architecture

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