TY - GEN
T1 - SCsafe
T2 - 22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016
AU - Duan, Yuelu
AU - Koufaty, David
AU - Torrellas, Josep
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/4/1
Y1 - 2016/4/1
N2 - Sequential Consistency Violations (SCV) in relaxed consistency machines cause programs to malfunction and are hard to debug. While there are proposals for detecting and recording SCVs, they are limited in that they end program execution after detecting the first SCV because the program is now non-SC. Therefore, they cannot be used in production runs. In addition, such proposals rely on complicated hardware. To address these problems, this paper proposes the first architecture that detects and logs SCVs in a continuous manner, while retaining SC. In addition, the scheme is precise and uses substantially simpler hardware. The scheme, called SCsafe, operates continously because, after SCV detection and logging, it recovers and resumes execution while retaining SC. As a result, it can be used in production runs. In addition, SCsafe is precise in that it identifies only true SCVs-rather than dependence cycles due to false sharing. Finally, SCsafe's hardware is mostly local to each processor, and uses known recovery techniques. We evaluate SCsafe using simulations of 16-processor multicores with Total Store Order or Release Consistency. In codes with SCVs, SCsafe detects and reports SCVs while enforcing SC during the execution. In codes with few SCVs, it adds a negligible performance overhead. Finally, SCsafe is scalable with the processor count.
AB - Sequential Consistency Violations (SCV) in relaxed consistency machines cause programs to malfunction and are hard to debug. While there are proposals for detecting and recording SCVs, they are limited in that they end program execution after detecting the first SCV because the program is now non-SC. Therefore, they cannot be used in production runs. In addition, such proposals rely on complicated hardware. To address these problems, this paper proposes the first architecture that detects and logs SCVs in a continuous manner, while retaining SC. In addition, the scheme is precise and uses substantially simpler hardware. The scheme, called SCsafe, operates continously because, after SCV detection and logging, it recovers and resumes execution while retaining SC. As a result, it can be used in production runs. In addition, SCsafe is precise in that it identifies only true SCVs-rather than dependence cycles due to false sharing. Finally, SCsafe's hardware is mostly local to each processor, and uses known recovery techniques. We evaluate SCsafe using simulations of 16-processor multicores with Total Store Order or Release Consistency. In codes with SCVs, SCsafe detects and reports SCVs while enforcing SC during the execution. In codes with few SCVs, it adds a negligible performance overhead. Finally, SCsafe is scalable with the processor count.
UR - http://www.scopus.com/inward/record.url?scp=84965036798&partnerID=8YFLogxK
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U2 - 10.1109/HPCA.2016.7446069
DO - 10.1109/HPCA.2016.7446069
M3 - Conference contribution
AN - SCOPUS:84965036798
T3 - Proceedings - International Symposium on High-Performance Computer Architecture
SP - 249
EP - 260
BT - Proceedings of the 2016 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2016
PB - IEEE Computer Society
Y2 - 12 March 2016 through 16 March 2016
ER -