Scratchpad memory optimizations for digital signal processing applications

Syed Z. Gilani, Nam Sung Kim, Michael Schulte

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Modern digital signal processors (DSPs) need to support a diverse array of applications ranging from digital filters to video decoding. Many of these applications have drastically different precision and on-chip memory requirements. Moreover, DSPs often employ aggressive dynamic voltage and frequency scaling (DVFS) techniques to minimize power consumption. However, at reduced voltages, process variations can significantly increase the failure rate of on-chip SRAMs designed with small transistors to achieve high integration density, resulting in low yields. Consequently, the size of transistors in SRAM cells and cell size needs to be increased to satisfy the target yield. However, this can result in high area overhead since on-chip memories consume a significant portion of the die area. In this paper, we present a scratchpad memory design that exploits the tradeoffs between SRAM cell sizes, their failure rates, the minimum operating voltage for target yield (V ddmin ), and application characteristics to achieve an on-chip memory area reduction of up to 17%. Our approach reduces V ddmin , which allows dynamic and leakage power savings of 42% and 36% respectively with DVFS. Moreover, for error-tolerant DSP applications we allow voltage scaling below V ddmin to achieve further power savings while incurring lower mean error as compared to short word-length memory. Finally, for error-sensitive applications, we propose a reconfigurable memory organization that trades memory capacity for higher precision at a lower V ddmin .

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
Pages974-979
Number of pages6
StatePublished - May 31 2011
Event14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 - Grenoble, France
Duration: Mar 14 2011Mar 18 2011

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
CountryFrance
CityGrenoble
Period3/14/113/18/11

    Fingerprint

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Gilani, S. Z., Kim, N. S., & Schulte, M. (2011). Scratchpad memory optimizations for digital signal processing applications. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 (pp. 974-979). [5763158] (Proceedings -Design, Automation and Test in Europe, DATE).