Graphene Nano-Ribbon Field-Effect Transistors (GNR-FETs) have emerged as promising next-generation devices. In particular, Schottky-barrier-type GNRFETs (SB-GNRFETs) have piqued interest due to their ambipolar I-V characteristics. Despite manufacturing successes, the lack of a SPICE-compatible compact model of SB-GNRFETs has hindered studies on evaluating the performance of this emerging technology on the circuit level. In this paper, we present the first SPICE-compatible model of SB-GNRFETs that takes various design parameters into account, which not only enables circuit-level simulations, but also provides a means to evaluate process variation, including effects of channel length, transistor width, oxide thickness, and graphene-specific edge roughness. With this model, we are able to explore the design space of SB-GNRFETs, evaluate delay and power performance of SB-GNRFET circuits, and compare them with conventional Si-CMOS and Metal-Oxide-Semiconductor-(MOS-)GNRFETs. Our study shows that SB-GNRFETs have higher speed and higher power dissipation, and have lower energy delay product than both Si-CMOS and MOS-GNRFETs, while MOS-GNRFETs are potentially good for low-power applications despite the presence of graphene-metal contact resistance that are not present in SB-GNRFET circuits. Two practical factors severely degrade the performance and even affect the functionality of SB-GNRFET circuits: 1) edge roughness and 2) limitation on operating point shifting.