TY - GEN

T1 - Scaling probabilistic timing verification of hardware using abstractions in design source code

AU - Kumar, Jayanand Asok

AU - Liu, Lingyi

AU - Vasudevan, Shobha

PY - 2011/12/1

Y1 - 2011/12/1

N2 - Sources of randomness such as physical process variations and input pattern variations make hardware timing a statistical measure. It is desirable to verify statistical timing properties at the higher levels of design such as the Register Transfer Level (RTL). The RTL design can be modeled as a Discrete Time Markov Chain (DTMC) and probabilistic model checking then applied to verify that the DTMC satisfies a desired timing specification. However, we find that such an approach does not scale beyond 10 10 states. In this paper, we introduce an abstraction methodology to scale this approach to large designs. Instead of considering the entire space of data values that can be assigned to the design input variables, we perform a value-based interval abstraction by considering only those intervals of input values that are relevant to a given timing property. We employ symbolic execution on the RTL source code to automatically derive such intervals for the design inputs, with respect to a given timing property. We use these intervals to construct smaller abstract DTMCs and thereby make the corresponding probabilistic model checking problems more tractable. We show that our abstraction is sound since we do not remove any probabilistic behavior that is relevant to the property of interest. We demonstrate the effectiveness of our technique using multiple designs used in communication systems such as FFT, filters and several modules of a real world H.264 decoder. We use our technique to successfully verify timing of an H.264 module, for which the concrete model contains more that 10 80 states, by constructing an abstract model with approximately only 10 10 states.

AB - Sources of randomness such as physical process variations and input pattern variations make hardware timing a statistical measure. It is desirable to verify statistical timing properties at the higher levels of design such as the Register Transfer Level (RTL). The RTL design can be modeled as a Discrete Time Markov Chain (DTMC) and probabilistic model checking then applied to verify that the DTMC satisfies a desired timing specification. However, we find that such an approach does not scale beyond 10 10 states. In this paper, we introduce an abstraction methodology to scale this approach to large designs. Instead of considering the entire space of data values that can be assigned to the design input variables, we perform a value-based interval abstraction by considering only those intervals of input values that are relevant to a given timing property. We employ symbolic execution on the RTL source code to automatically derive such intervals for the design inputs, with respect to a given timing property. We use these intervals to construct smaller abstract DTMCs and thereby make the corresponding probabilistic model checking problems more tractable. We show that our abstraction is sound since we do not remove any probabilistic behavior that is relevant to the property of interest. We demonstrate the effectiveness of our technique using multiple designs used in communication systems such as FFT, filters and several modules of a real world H.264 decoder. We use our technique to successfully verify timing of an H.264 module, for which the concrete model contains more that 10 80 states, by constructing an abstract model with approximately only 10 10 states.

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M3 - Conference contribution

AN - SCOPUS:84863255428

SN - 9781467308960

T3 - 2011 Formal Methods in Computer-Aided Design, FMCAD 2011

SP - 196

EP - 205

BT - 2011 Formal Methods in Computer-Aided Design, FMCAD 2011

T2 - 2011 Formal Methods in Computer-Aided Design, FMCAD 2011

Y2 - 30 October 2011 through 2 November 2011

ER -