ScalCore: Designing a core for voltage scalability

Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, Asit Mishra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Upcoming multicores need to provide increasingly stringent energy-efficient execution modes. Currently, energy efficiency is attained by lowering the voltage (Vdd) through DVFS. However, the effectiveness of DVFS is limited: designing cores for low Vdd results in energy inefficiency at nominal Vdd. Our goal is to design a core for Voltage Scalability, i.e., one that can work in high-performance mode (HPMode) at nominal Vdd, and in a very energy-efficient mode (EEMode) at low Vdd. We call this core ScalCore. To operate energy-efficiently in EEMode, ScalCore introduces two ideas. First, since logic and storage structures scale differently with Vdd, ScalCore applies two low Vdds to the pipeline: one to the logic stages (Vlogic) and a higher one to storage-intensive stages. Secondly, ScalCore further increases the low Vdd of the storage-intensive stages (Vop), so that they are substantially faster than the logic ones. Then, it exploits the speed differential by either fusing storage-intensive pipeline stages or increasing the size of storage structures in the pipeline. Our simulations of 16 cores show that a design with Scal-Cores in EEMode is much more energy-efficient than one with conventional cores and aggressive DVFS: for approximately the same power, ScalCores reduce the average execution time of programs by 31%, the energy (E) consumed by 48%, and the ED product by 60%. In addition, dynamically switching between EEMode and HPMode based on program phases is very effective: it reduces the average execution time and ED product by a further 28% and 15%, respectively.

Original languageEnglish (US)
Title of host publicationProceedings of the 2016 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2016
PublisherIEEE Computer Society
Pages681-693
Number of pages13
ISBN (Electronic)9781467392112
DOIs
StatePublished - Apr 1 2016
Event22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016 - Barcelona, Spain
Duration: Mar 12 2016Mar 16 2016

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume2016-April
ISSN (Print)1530-0897

Other

Other22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016
CountrySpain
CityBarcelona
Period3/12/163/16/16

ASJC Scopus subject areas

  • Hardware and Architecture

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  • Cite this

    Gopireddy, B., Song, C., Torrellas, J., Kim, N. S., Agrawal, A., & Mishra, A. (2016). ScalCore: Designing a core for voltage scalability. In Proceedings of the 2016 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2016 (pp. 681-693). [7446104] (Proceedings - International Symposium on High-Performance Computer Architecture; Vol. 2016-April). IEEE Computer Society. https://doi.org/10.1109/HPCA.2016.7446104