Abstract
A new search-based satisfiability (SAT) formulation that can handle entire field programmable gate array (FPGA), routing all nets concurrently is presented. The approach relies on a recently developed SAT engine that uses systematic search with conflict directed nonchronological backtracking, capable of handling very large SAT instances. Preliminary experimental results suggest that this approach to FPGA routing is more viable than earlier binary decision diagram-based method.
Original language | English (US) |
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Pages | 167-175 |
Number of pages | 9 |
State | Published - 1999 |
Externally published | Yes |
Event | Proceedings of the 1999 ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA-99 - Monterey, CA, USA Duration: Feb 21 1999 → Feb 23 1999 |
Conference
Conference | Proceedings of the 1999 ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA-99 |
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City | Monterey, CA, USA |
Period | 2/21/99 → 2/23/99 |
ASJC Scopus subject areas
- General Computer Science