Satisfiability-based layout revisited: Detailed routing of complex FPGAs via search-based Boolean SAT

Gi Joon Nam, Karem A. Sakallah, Rob A. Rutenbar

Research output: Contribution to conferencePaperpeer-review

Abstract

A new search-based satisfiability (SAT) formulation that can handle entire field programmable gate array (FPGA), routing all nets concurrently is presented. The approach relies on a recently developed SAT engine that uses systematic search with conflict directed nonchronological backtracking, capable of handling very large SAT instances. Preliminary experimental results suggest that this approach to FPGA routing is more viable than earlier binary decision diagram-based method.

Original languageEnglish (US)
Pages167-175
Number of pages9
StatePublished - Jan 1 1999
EventProceedings of the 1999 ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA-99 - Monterey, CA, USA
Duration: Feb 21 1999Feb 23 1999

Conference

ConferenceProceedings of the 1999 ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA-99
CityMonterey, CA, USA
Period2/21/992/23/99

ASJC Scopus subject areas

  • Computer Science(all)

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