Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm

Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Because of complexity of analog circuits, their verification presents many challenges. We propose a runtime verification algorithm to verify design properties of nonlinear analog circuits. Our algorithm is based on performing exploratory simulations in the state-time space using the Time-augmented Rapidly Exploring Random Tree (TRRT) algorithm. The proposed runtime verification methodology consists of i) incremental construction of the TRRT to explore the state-time space and ii) use of an incremental online monitoring algorithm to check whether or not the incremented TRRT satisfies or violates specification properties at each iteration. In comparison to the Monte Carlo simulations, for providing the same state-space coverage, we utilize a logarithmic order of memory and time.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2013
Pages21-26
Number of pages6
StatePublished - Oct 21 2013
Event16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France
Duration: Mar 18 2013Mar 22 2013

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
CountryFrance
CityGrenoble
Period3/18/133/22/13

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm'. Together they form a unique fingerprint.

Cite this