TY - GEN
T1 - Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm
AU - Ahmadyan, Seyed Nematollah
AU - Kumar, Jayanand Asok
AU - Vasudevan, Shobha
PY - 2013
Y1 - 2013
N2 - Because of complexity of analog circuits, their verification presents many challenges. We propose a runtime verification algorithm to verify design properties of nonlinear analog circuits. Our algorithm is based on performing exploratory simulations in the state-time space using the Time-augmented Rapidly Exploring Random Tree (TRRT) algorithm. The proposed runtime verification methodology consists of i) incremental construction of the TRRT to explore the state-time space and ii) use of an incremental online monitoring algorithm to check whether or not the incremented TRRT satisfies or violates specification properties at each iteration. In comparison to the Monte Carlo simulations, for providing the same state-space coverage, we utilize a logarithmic order of memory and time.
AB - Because of complexity of analog circuits, their verification presents many challenges. We propose a runtime verification algorithm to verify design properties of nonlinear analog circuits. Our algorithm is based on performing exploratory simulations in the state-time space using the Time-augmented Rapidly Exploring Random Tree (TRRT) algorithm. The proposed runtime verification methodology consists of i) incremental construction of the TRRT to explore the state-time space and ii) use of an incremental online monitoring algorithm to check whether or not the incremented TRRT satisfies or violates specification properties at each iteration. In comparison to the Monte Carlo simulations, for providing the same state-space coverage, we utilize a logarithmic order of memory and time.
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U2 - 10.7873/date.2013.019
DO - 10.7873/date.2013.019
M3 - Conference contribution
AN - SCOPUS:84885656490
SN - 9783981537000
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 21
EP - 26
BT - Proceedings - Design, Automation and Test in Europe, DATE 2013
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
Y2 - 18 March 2013 through 22 March 2013
ER -