TY - GEN
T1 - Runnemede
T2 - 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
AU - Carter, Nicholas P.
AU - Agrawal, Aditya
AU - Borkar, Shekhar
AU - Cledat, Romain
AU - David, Howard
AU - Dunning, Dave
AU - Fryman, Joshua
AU - Ganev, Ivan
AU - Golliver, Roger A.
AU - Knauerhase, Rob
AU - Lethin, Richard
AU - Meister, Benoit
AU - Mishra, Asit K.
AU - Pinfold, Wilfred R.
AU - Teller, Justin
AU - Torrellas, Josep
AU - Vasilache, Nicolas
AU - Venkatesh, Ganesh
AU - Xu, Jianping
PY - 2013
Y1 - 2013
N2 - DARPA's Ubiquitous High-Performance Computing (UHPC) program asked researchers to develop computing systems capable of achieving energy efficiencies of 50 GOPS/Watt, assuming 2018-era fabrication technologies. This paper describes Runnemede, the research architecture developed by the Intel-led UHPC team. Runnemede is being developed through a co-design process that considers the hardware, the runtime/OS, and applications simultaneously. Near-threshold voltage operation, fine-grained power and clock management, and separate execution units for runtime and application code are used to reduce energy consumption. Memory energy is minimized through application-managed on-chip memory and direct physical addressing. A hierarchical on-chip network reduces communication energy, and a codelet-based execution model supports extreme parallelism and fine-grained tasks. We present an initial evaluation of Runnemede that shows the design process for our on-chip network, demonstrates 2-4x improvements in memory energy from explicit control of on-chip memory, and illustrates the impact of hardware-software co-design on the energy consumption of a synthetic aperture radar algorithm on our architecture.
AB - DARPA's Ubiquitous High-Performance Computing (UHPC) program asked researchers to develop computing systems capable of achieving energy efficiencies of 50 GOPS/Watt, assuming 2018-era fabrication technologies. This paper describes Runnemede, the research architecture developed by the Intel-led UHPC team. Runnemede is being developed through a co-design process that considers the hardware, the runtime/OS, and applications simultaneously. Near-threshold voltage operation, fine-grained power and clock management, and separate execution units for runtime and application code are used to reduce energy consumption. Memory energy is minimized through application-managed on-chip memory and direct physical addressing. A hierarchical on-chip network reduces communication energy, and a codelet-based execution model supports extreme parallelism and fine-grained tasks. We present an initial evaluation of Runnemede that shows the design process for our on-chip network, demonstrates 2-4x improvements in memory energy from explicit control of on-chip memory, and illustrates the impact of hardware-software co-design on the energy consumption of a synthetic aperture radar algorithm on our architecture.
UR - http://www.scopus.com/inward/record.url?scp=84880323875&partnerID=8YFLogxK
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U2 - 10.1109/HPCA.2013.6522319
DO - 10.1109/HPCA.2013.6522319
M3 - Conference contribution
AN - SCOPUS:84880323875
SN - 9781467355858
T3 - Proceedings - International Symposium on High-Performance Computer Architecture
SP - 198
EP - 209
BT - 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
Y2 - 23 February 2013 through 27 February 2013
ER -