Run-time spatial locality detection and optimization

Teresa L. Johnson, Matthew C. Merten, Wen-Mei W Hwu

Research output: Contribution to journalArticle

Abstract

As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, latency hiding techniques are critical for improved application performance on future processors. We present a microarchitecture scheme which detects and adapts to varying spatial locality, dynamically adjusting the amount of data fetched on a cache miss. The Spatial Locality Detection Table, introduced in this paper, facilitates the detection of spatial locality across adjacent cached blocks. Results from detailed simulations of several integer programs show significant speedups. The improvements are due to the reduction of conflict and capacity misses by utilizing small blocks and small fetch sizes when spatial locality is absent, and the prefetching effect of large fetch sizes when spatial locality exists.

Original languageEnglish (US)
Pages (from-to)57-64
Number of pages8
JournalProceedings of the Annual International Symposium on Microarchitecture
StatePublished - 1997

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

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Run-time spatial locality detection and optimization. / Johnson, Teresa L.; Merten, Matthew C.; Hwu, Wen-Mei W.

In: Proceedings of the Annual International Symposium on Microarchitecture, 1997, p. 57-64.

Research output: Contribution to journalArticle

@article{2abdd4514ae54fdeb5576e5234d55480,
title = "Run-time spatial locality detection and optimization",
abstract = "As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, latency hiding techniques are critical for improved application performance on future processors. We present a microarchitecture scheme which detects and adapts to varying spatial locality, dynamically adjusting the amount of data fetched on a cache miss. The Spatial Locality Detection Table, introduced in this paper, facilitates the detection of spatial locality across adjacent cached blocks. Results from detailed simulations of several integer programs show significant speedups. The improvements are due to the reduction of conflict and capacity misses by utilizing small blocks and small fetch sizes when spatial locality is absent, and the prefetching effect of large fetch sizes when spatial locality exists.",
author = "Johnson, {Teresa L.} and Merten, {Matthew C.} and Hwu, {Wen-Mei W}",
year = "1997",
language = "English (US)",
pages = "57--64",
journal = "Proceedings of the Annual International Symposium on Microarchitecture, MICRO",
issn = "1072-4451",

}

TY - JOUR

T1 - Run-time spatial locality detection and optimization

AU - Johnson, Teresa L.

AU - Merten, Matthew C.

AU - Hwu, Wen-Mei W

PY - 1997

Y1 - 1997

N2 - As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, latency hiding techniques are critical for improved application performance on future processors. We present a microarchitecture scheme which detects and adapts to varying spatial locality, dynamically adjusting the amount of data fetched on a cache miss. The Spatial Locality Detection Table, introduced in this paper, facilitates the detection of spatial locality across adjacent cached blocks. Results from detailed simulations of several integer programs show significant speedups. The improvements are due to the reduction of conflict and capacity misses by utilizing small blocks and small fetch sizes when spatial locality is absent, and the prefetching effect of large fetch sizes when spatial locality exists.

AB - As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, latency hiding techniques are critical for improved application performance on future processors. We present a microarchitecture scheme which detects and adapts to varying spatial locality, dynamically adjusting the amount of data fetched on a cache miss. The Spatial Locality Detection Table, introduced in this paper, facilitates the detection of spatial locality across adjacent cached blocks. Results from detailed simulations of several integer programs show significant speedups. The improvements are due to the reduction of conflict and capacity misses by utilizing small blocks and small fetch sizes when spatial locality is absent, and the prefetching effect of large fetch sizes when spatial locality exists.

UR - http://www.scopus.com/inward/record.url?scp=0031364102&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031364102&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0031364102

SP - 57

EP - 64

JO - Proceedings of the Annual International Symposium on Microarchitecture, MICRO

JF - Proceedings of the Annual International Symposium on Microarchitecture, MICRO

SN - 1072-4451

ER -