Abstract
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, latency hiding techniques are critical for improved application performance on future processors. We present a microarchitecture scheme which detects and adapts to varying spatial locality, dynamically adjusting the amount of data fetched on a cache miss. The Spatial Locality Detection Table, introduced in this paper, facilitates the detection of spatial locality across adjacent cached blocks. Results from detailed simulations of several integer programs show significant speedups. The improvements are due to the reduction of conflict and capacity misses by utilizing small blocks and small fetch sizes when spatial locality is absent, and the prefetching effect of large fetch sizes when spatial locality exists.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 57-64 |
| Number of pages | 8 |
| Journal | Proceedings of the Annual International Symposium on Microarchitecture |
| State | Published - 1997 |
| Event | Proceedings of the 1997 30th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-30 - Triangle Park, NC, USA Duration: Dec 1 1997 → Dec 3 1997 |
ASJC Scopus subject areas
- Hardware and Architecture
- Software