The VAX architecture is a popular ISP architecture that has been implemented in several different technologies targeted to a wide range of performance specifications. However, it has been argued that the VAX has specific characteristics which preclude a very high performance implementation. The authors have developed the HPS microarchitecture which is specifically intended for implementing very high performance computing engines. The model of execution is a restriction on fine granularity data flow. The authors concentrate on one particular aspect of an HPS implementation of the VAX architecture: the generation of HPS microinstructions (i. e. , data flow nodes) from a VAX instruction stream.