@inproceedings{560683f1a4e3466399835060eceac41e,
title = "RUN-TIME GENERATION OF HPS MICROINSTRUCTIONS FROM A VAX INSTRUCTION STREAM.",
abstract = "The VAX architecture is a popular ISP architecture that has been implemented in several different technologies targeted to a wide range of performance specifications. However, it has been argued that the VAX has specific characteristics which preclude a very high performance implementation. The authors have developed the HPS microarchitecture which is specifically intended for implementing very high performance computing engines. The model of execution is a restriction on fine granularity data flow. The authors concentrate on one particular aspect of an HPS implementation of the VAX architecture: the generation of HPS microinstructions (i. e. , data flow nodes) from a VAX instruction stream.",
author = "Patt, {Yale N.} and Melvin, {Stephen W.} and Hwu, {Wen mei} and Shebanow, {Michael C.} and Chien Chen and Jiajuin We",
year = "1986",
doi = "10.1145/19551.19539",
language = "English (US)",
isbn = "081860736X",
series = "MICRO: Annual Microprogramming Workshop",
publisher = "IEEE",
pages = "75--81",
booktitle = "MICRO",
}