RUN-TIME GENERATION OF HPS MICROINSTRUCTIONS FROM A VAX INSTRUCTION STREAM.

Yale N. Patt, Stephen W. Melvin, Wen mei Hwu, Michael C. Shebanow, Chien Chen, Jiajuin We

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The VAX architecture is a popular ISP architecture that has been implemented in several different technologies targeted to a wide range of performance specifications. However, it has been argued that the VAX has specific characteristics which preclude a very high performance implementation. The authors have developed the HPS microarchitecture which is specifically intended for implementing very high performance computing engines. The model of execution is a restriction on fine granularity data flow. The authors concentrate on one particular aspect of an HPS implementation of the VAX architecture: the generation of HPS microinstructions (i. e. , data flow nodes) from a VAX instruction stream.

Original languageEnglish (US)
Title of host publicationMICRO
Subtitle of host publicationAnnual Microprogramming Workshop
PublisherIEEE
Pages75-81
Number of pages7
ISBN (Print)081860736X, 9780818607363
DOIs
StatePublished - 1986
Externally publishedYes

Publication series

NameMICRO: Annual Microprogramming Workshop
ISSN (Print)0361-2163

ASJC Scopus subject areas

  • Engineering(all)

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