Abstract
Cache effectiveness should be improved to deal with long memory latencies, to utilize run-time adaptive cache management techniques, to optimize both performance and cost of implementation, and to increase data cache effectiveness for integer programs. A microarchitecture scheme where the hardware determines the data placement is presented based on dynamic referencing behavior. This scheme is fully compatible with instruction set architectures. Run-time adaptive cache management can significantly improve the overall performance of integer applications. The improvements are due to increased cache miss handling latencies.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 774-775 |
| Number of pages | 2 |
| Journal | Proceedings of the Hawaii International Conference on System Sciences |
| Volume | 7 |
| State | Published - 1998 |
| Event | Proceedings of the 1998 31st Annual Hawaii International Conference on System Sciences. Part 1 (of 7) - Big Island, HI, USA Duration: Jan 6 1998 → Jan 9 1998 |
ASJC Scopus subject areas
- General Computer Science