Run-time adaptive cache hierarchy management via reference analysis

Teresa L. Johnson, Wen mei W. Hwu

Research output: Contribution to journalConference article

Abstract

Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap between processor and main memory performance is expected to grow, increasing the number of execution cycles spent waiting for memory accesses to complete. One solution to this growing problem is to reduce the number of cache misses by increasing the effectiveness of the cache hierarchy. In this paper we present a technique for dynamic analysis of program data access behavior, which is then used to proactively guide the placement of data within the cache hierarchy in a location-sensitive manner. We introduce the concept of a macroblock, which allows us to feasibly characterize the memory locations accessed by a program, and a Memory Address Table, which performs the dynamic reference analysis. Our technique is fully compatible with existing Instruction Set Architectures. Results from detailed simulations of several integer programs show significant speedups.

Original languageEnglish (US)
Pages (from-to)315-326
Number of pages12
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
StatePublished - Jan 1 1997
EventProceedings of the 1997 24th Annual International Symposium on Computer Architecture - Denver, CO, USA
Duration: Jun 2 1997Jun 4 1997

Fingerprint

Data storage equipment
Dynamic analysis
Clocks

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Run-time adaptive cache hierarchy management via reference analysis. / Johnson, Teresa L.; Hwu, Wen mei W.

In: Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA, 01.01.1997, p. 315-326.

Research output: Contribution to journalConference article

@article{3a6443a6b6d94a6b9038d1462c551aae,
title = "Run-time adaptive cache hierarchy management via reference analysis",
abstract = "Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap between processor and main memory performance is expected to grow, increasing the number of execution cycles spent waiting for memory accesses to complete. One solution to this growing problem is to reduce the number of cache misses by increasing the effectiveness of the cache hierarchy. In this paper we present a technique for dynamic analysis of program data access behavior, which is then used to proactively guide the placement of data within the cache hierarchy in a location-sensitive manner. We introduce the concept of a macroblock, which allows us to feasibly characterize the memory locations accessed by a program, and a Memory Address Table, which performs the dynamic reference analysis. Our technique is fully compatible with existing Instruction Set Architectures. Results from detailed simulations of several integer programs show significant speedups.",
author = "Johnson, {Teresa L.} and Hwu, {Wen mei W.}",
year = "1997",
month = "1",
day = "1",
language = "English (US)",
pages = "315--326",
journal = "Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA",
issn = "1063-6897",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Run-time adaptive cache hierarchy management via reference analysis

AU - Johnson, Teresa L.

AU - Hwu, Wen mei W.

PY - 1997/1/1

Y1 - 1997/1/1

N2 - Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap between processor and main memory performance is expected to grow, increasing the number of execution cycles spent waiting for memory accesses to complete. One solution to this growing problem is to reduce the number of cache misses by increasing the effectiveness of the cache hierarchy. In this paper we present a technique for dynamic analysis of program data access behavior, which is then used to proactively guide the placement of data within the cache hierarchy in a location-sensitive manner. We introduce the concept of a macroblock, which allows us to feasibly characterize the memory locations accessed by a program, and a Memory Address Table, which performs the dynamic reference analysis. Our technique is fully compatible with existing Instruction Set Architectures. Results from detailed simulations of several integer programs show significant speedups.

AB - Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap between processor and main memory performance is expected to grow, increasing the number of execution cycles spent waiting for memory accesses to complete. One solution to this growing problem is to reduce the number of cache misses by increasing the effectiveness of the cache hierarchy. In this paper we present a technique for dynamic analysis of program data access behavior, which is then used to proactively guide the placement of data within the cache hierarchy in a location-sensitive manner. We introduce the concept of a macroblock, which allows us to feasibly characterize the memory locations accessed by a program, and a Memory Address Table, which performs the dynamic reference analysis. Our technique is fully compatible with existing Instruction Set Architectures. Results from detailed simulations of several integer programs show significant speedups.

UR - http://www.scopus.com/inward/record.url?scp=0030717768&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030717768&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0030717768

SP - 315

EP - 326

JO - Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

JF - Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

SN - 1063-6897

ER -