An array of rolled-up power inductors for on-chip applications comprises at least two rolled-up power inductors connected in series and formed from a stack of multilayer sheets. The array includes a first rolled-up power inductor comprising a first multilayer sheet in a rolled configuration about a first longitudinal axis and second rolled-up power inductor comprising a second multilayer sheet in a rolled configuration about a second longitudinal axis. The first and second rolled-up power inductors are laterally spaced apart. The first multilayer sheet comprises a first patterned conductive layer on a first strain-relieved layer, and the second multilayer sheet comprises a second patterned conductive layer on a second strain-relieved layer. Prior to roll-up of the second and first multilayer sheets, the second multilayer sheet is disposed on the first multilayer sheet, and a through-thickness first via connects the second patterned conductive layer with the first patterned conductive layer.
|U.S. patent number
|Published - Nov 26 2019