Rigel: An architecture and scalable programming interface for a 1000-core accelerator

John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal C. Crago, William Tuohy, Aqeel Mahesri, Steven Sam Lumetta, Matthew I. Frank, Sanjay Jeram Patel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper considers Rigel, a programmable accelerator architecture for a broad class of data- and task-parallel computation. Rigel comprises 1000+ hierarchically-organized cores that use a fine-grained, dynamically scheduled single-program, multiple-data (SPMD) execution model. Rigel's low-level programming interface adopts a single global address space model where parallel work is expressed in a task-centric, bulk-synchronized manner using minimal hardware support. Compared to existing accelerators, which contain domain-specific hardware, specialized memories, and restrictive programming models, Rigel is more flexible and provides a straightforward target for a broader set of applications. We perform a design analysis of Rigel to quantify the compute density and power efficiency of our initial design. We find that Rigel can achieve a density of over 8 single-precision GFLOPS/mm2 in 45nm, which is comparable to high-end GPUs scaled to 45nm. We perform experimental analysis on several applications ported to the Rigel low-level programming interface. We examine scalability issues related to work distribution, synchronization, and load-balancing for 1000-core accelerators using software techniques and minimal specialized hardware support. We find that while it is important to support fast task distribution and barrier operations, these operations can be implemented without specialized hardware using flexible hardware primitives.

Original languageEnglish (US)
Title of host publicationISCA 2009 - 36th Annual International Symposium on Computer Architecture, Conference Proceedings
Pages140-151
Number of pages12
DOIs
StatePublished - Nov 30 2009
EventISCA 2009 - 36th Annual International Symposium on Computer Architecture - Austin, TX, United States
Duration: Jun 20 2009Jun 24 2009

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

OtherISCA 2009 - 36th Annual International Symposium on Computer Architecture
Country/TerritoryUnited States
CityAustin, TX
Period6/20/096/24/09

Keywords

  • Accelerator
  • Computer architecture
  • Low-level programming interface

ASJC Scopus subject areas

  • Hardware and Architecture

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