Rigel: A 1,024-core single-chip accelerator architecture

Daniel R. Johnson, Matthew R. Johnson, John H. Kelm, William Tuohy, Steven S. Lumetta, Sanjay J. Patel

Research output: Contribution to journalArticlepeer-review


Rigel is a single-chip accelerator architecture with 1,024 independent processing cores targeted at a broad class of data- and task-parallel computation. This article discusses Rigel's motivation, evaluates its performance scalability as well as power and area requirements, and explores memory systems in the context of 1,024-core single-chip accelerators. The authors also consider future opportunities and challenges for large-scale designs.

Original languageEnglish (US)
Article number5871571
Pages (from-to)30-41
Number of pages12
JournalIEEE Micro
Issue number4
StatePublished - Jul 2011


  • Multiple data-stream architectures (multiprocessors)
  • multicore
  • multiple data processors
  • multiple instruction
  • parallel architectures
  • parallel processors
  • single-chip multiprocessors

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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