Rigel: A 1,024-core single-chip accelerator architecture

Daniel R. Johnson; Matthew R. Johnson; John H. Kelm; William Tuohy; Steven S. Lumetta; Sanjay J. Patel

doi:10.1109/MM.2011.40

Rigel: A 1,024-core single-chip accelerator architecture

Daniel R. Johnson, Matthew R. Johnson, John H. Kelm, William Tuohy, Steven S. Lumetta, Sanjay J. Patel

Research output: Contribution to journal › Article › peer-review

Abstract

Rigel is a single-chip accelerator architecture with 1,024 independent processing cores targeted at a broad class of data- and task-parallel computation. This article discusses Rigel's motivation, evaluates its performance scalability as well as power and area requirements, and explores memory systems in the context of 1,024-core single-chip accelerators. The authors also consider future opportunities and challenges for large-scale designs.

Original language	English (US)
Article number	5871571
Pages (from-to)	30-41
Number of pages	12
Journal	IEEE Micro
Volume	31
Issue number	4
DOIs	https://doi.org/10.1109/MM.2011.40
State	Published - Jul 2011

Keywords

Multiple data-stream architectures (multiprocessors)
multicore
multiple data processors
multiple instruction
parallel architectures
parallel processors
single-chip multiprocessors

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2011.40

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Rigel: A 1,024-core single-chip accelerator architecture

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Keywords

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