Reverse biasing logic circuit

Sung Mo (Steve) Kang (Inventor), Seung-Moon (Scott) Yoo (Inventor)

Research output: Patent


A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.
Original languageEnglish (US)
U.S. patent number6759873
Filing date5/21/02
StatePublished - Jul 6 2004


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