TY - GEN
T1 - Revec
T2 - 28th International Conference on Compiler Construction, CC 2019
AU - Mendis, Charith
AU - Jain, Ajay
AU - Jain, Paras
AU - Amarasinghe, Saman
N1 - Publisher Copyright:
© 2019 Copyright held by the owner/author(s).
PY - 2019/2/16
Y1 - 2019/2/16
N2 - Modern microprocessors are equipped with Single Instruction Multiple Data (SIMD) or vector instructions which expose data level parallelism at a fine granularity. Programmers exploit this parallelism by using low-level vector intrinsics in their code. However, once programs are written using vector intrinsics of a specific instruction set, the code becomes non-portable. Modern compilers are unable to analyze and retarget the code to newer vector instruction sets. Hence, programmers have to manually rewrite the same code using vector intrinsics of a newer generation to exploit higher data widths and capabilities of new instruction sets. This process is tedious, error-prone and requires maintaining multiple code bases. We propose Revec, a compiler optimization pass which revectorizes already vectorized code, by retargeting it to use vector instructions of newer generations. The transformation is transparent, happening at the compiler intermediate representation level, and enables performance portability of hand-vectorized code. Revec can achieve performance improvements in real-world performance critical kernels. In particular, Revec achieves geometric mean speedups of 1.160× and 1.430× on fast integer unpacking kernels, and speedups of 1.145× and 1.195× on hand-vectorized x265 media codec kernels when retargeting their SSE-series implementations to use AVX2 and AVX-512 vector instructions respectively. We also extensively test Revec’s impact on 216 intrinsic-rich implementations of image processing and stencil kernels relative to hand-retargeting.
AB - Modern microprocessors are equipped with Single Instruction Multiple Data (SIMD) or vector instructions which expose data level parallelism at a fine granularity. Programmers exploit this parallelism by using low-level vector intrinsics in their code. However, once programs are written using vector intrinsics of a specific instruction set, the code becomes non-portable. Modern compilers are unable to analyze and retarget the code to newer vector instruction sets. Hence, programmers have to manually rewrite the same code using vector intrinsics of a newer generation to exploit higher data widths and capabilities of new instruction sets. This process is tedious, error-prone and requires maintaining multiple code bases. We propose Revec, a compiler optimization pass which revectorizes already vectorized code, by retargeting it to use vector instructions of newer generations. The transformation is transparent, happening at the compiler intermediate representation level, and enables performance portability of hand-vectorized code. Revec can achieve performance improvements in real-world performance critical kernels. In particular, Revec achieves geometric mean speedups of 1.160× and 1.430× on fast integer unpacking kernels, and speedups of 1.145× and 1.195× on hand-vectorized x265 media codec kernels when retargeting their SSE-series implementations to use AVX2 and AVX-512 vector instructions respectively. We also extensively test Revec’s impact on 216 intrinsic-rich implementations of image processing and stencil kernels relative to hand-retargeting.
KW - Optimizing compilation
KW - Program rejuvenation
KW - Single Instruction Multiple Data (SIMD)
KW - Vectorization
UR - https://www.scopus.com/pages/publications/85062259667
UR - https://www.scopus.com/pages/publications/85062259667#tab=citedBy
U2 - 10.1145/3302516.3307357
DO - 10.1145/3302516.3307357
M3 - Conference contribution
AN - SCOPUS:85062259667
T3 - ACM International Conference Proceeding Series
SP - 29
EP - 41
BT - CC 2019 - Proceedings of the 28th International Conference on Compiler Construction
A2 - Kulkarni, Milind
A2 - Amaral, J. Nelson
PB - Association for Computing Machinery
Y2 - 16 February 2019 through 17 February 2019
ER -