TY - GEN
T1 - Rethinking Programmable Earable Processors
AU - Bleier, Nathaniel
AU - Mubarik, Muhammad Husnain
AU - Chakraborty, Srijan
AU - Kishore, Shreyas
AU - Kumar, Rakesh
N1 - Publisher Copyright:
© 2022 Copyright held by the owner/author(s). Publication rights licensed to ACM.
PY - 2022/6/18
Y1 - 2022/6/18
N2 - Earables such as earphones [15, 16, 73], hearing aids [28], and smart glasses [2, 14] are poised to be a prominent programmable computing platform in the future. In this paper, we ask the question: what kind of programmable hardware would be needed to support earable computing in future? To understand hardware requirements, we propose EarBench, a suite of representative emerging earable applications with diverse sensor-based inputs and computation requirements. Our analysis of EarBench applications shows that, on average, there is a 13.54×-3.97× performance gap between the computational needs of EarBench applications and the performance of the microprocessors that several of today's programmable earable SoCs are based on; more complex microprocessors have unacceptable energy efciency for Earable applications. Our analysis also shows that EarBench applications are dominated by a small number of digital signal processing (DSP) and machine learning (ML)-based kernels that have signifcant computational similarity. We propose SpEaC-a coarse-grained reconfgurable spatial architecture-as an energy-efcient programmable processor for earable applications. SpEaC targets earable applications efciently using a) a reconfgurable fxed-point multiply-and-add augmented reduction tree-based substrate with support for vectorized complex operations that is optimized for the earable ML and DSP kernel code and b) a tightly coupled control core for executing other code (including non-matrix computation, or non-multiply or add operations in the earable DSP kernel code). Unlike other CGRAs that typically target general-purpose computations, SpEaC substrate is optimized for energy-efcient execution of the earable kernels at the expense of generality. Across all our kernels, SpEaC outperforms programmable cores modeled after M4, M7, A53, and HiFi4 DSP by 99.3×, 32.5×, 14.8×, and 9.8× respectively. At 63 mW in 28 nm, the energy efciency benefts are 1.55×, 9.04×, 68.3×, and 32.7× respectively; energy efciency benefts are 15.7×-1087× over a low power Mali T628 MP6 GPU.
AB - Earables such as earphones [15, 16, 73], hearing aids [28], and smart glasses [2, 14] are poised to be a prominent programmable computing platform in the future. In this paper, we ask the question: what kind of programmable hardware would be needed to support earable computing in future? To understand hardware requirements, we propose EarBench, a suite of representative emerging earable applications with diverse sensor-based inputs and computation requirements. Our analysis of EarBench applications shows that, on average, there is a 13.54×-3.97× performance gap between the computational needs of EarBench applications and the performance of the microprocessors that several of today's programmable earable SoCs are based on; more complex microprocessors have unacceptable energy efciency for Earable applications. Our analysis also shows that EarBench applications are dominated by a small number of digital signal processing (DSP) and machine learning (ML)-based kernels that have signifcant computational similarity. We propose SpEaC-a coarse-grained reconfgurable spatial architecture-as an energy-efcient programmable processor for earable applications. SpEaC targets earable applications efciently using a) a reconfgurable fxed-point multiply-and-add augmented reduction tree-based substrate with support for vectorized complex operations that is optimized for the earable ML and DSP kernel code and b) a tightly coupled control core for executing other code (including non-matrix computation, or non-multiply or add operations in the earable DSP kernel code). Unlike other CGRAs that typically target general-purpose computations, SpEaC substrate is optimized for energy-efcient execution of the earable kernels at the expense of generality. Across all our kernels, SpEaC outperforms programmable cores modeled after M4, M7, A53, and HiFi4 DSP by 99.3×, 32.5×, 14.8×, and 9.8× respectively. At 63 mW in 28 nm, the energy efciency benefts are 1.55×, 9.04×, 68.3×, and 32.7× respectively; energy efciency benefts are 15.7×-1087× over a low power Mali T628 MP6 GPU.
UR - https://www.scopus.com/pages/publications/85132841105
UR - https://www.scopus.com/pages/publications/85132841105#tab=citedBy
U2 - 10.1145/3470496.3527396
DO - 10.1145/3470496.3527396
M3 - Conference contribution
AN - SCOPUS:85132841105
T3 - Proceedings - International Symposium on Computer Architecture
SP - 454
EP - 467
BT - ISCA 2022 - Proceedings of the 49th Annual International Symposium on Computer Architecture
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 49th IEEE/ACM International Symposium on Computer Architecture, ISCA 2022
Y2 - 18 June 2022 through 22 June 2022
ER -