TY - GEN
T1 - Restructuring programs for high-speed computers with Polaris
AU - Blume, Bill
AU - Eigenmann, Rudolf
AU - Faigin, Keith
AU - Grout, John
AU - Lee, Jaejin
AU - Lawrence, Tom
AU - Hoeflinger, Jay
AU - Padua, David
AU - Paek, Yunheung
AU - Petersen, Paul
AU - Pottenger, Bill
AU - Rauchwerger, Lawrence
AU - Tu, Peng
AU - Weatherford, Stephen
N1 - Publisher Copyright:
© 1996 IEEE.
PY - 1996
Y1 - 1996
N2 - The ability to automatically parallelize standard programming languages results in program portability across a wide range of machine architectures. It is the goal of the Polaris project to develop a new parallelizing compiler that overcomes limitations of current compilers. While current parallelizing compilers may succeed on small kernels, they often fail to extract any meaningful parallelism from whole applications. After a study of application codes, it was concluded that by adding a few new techniques to current compilers, automatic parallelization becomes feasible for a range of whole applications. The techniques needed are interprocedural analysis, scalar and array privatization, symbolic dependence analysis, and advanced induction and reduction recognition and elimination, along with run-time techniques to permit the parallelization of loops with unknown dependence relations.
AB - The ability to automatically parallelize standard programming languages results in program portability across a wide range of machine architectures. It is the goal of the Polaris project to develop a new parallelizing compiler that overcomes limitations of current compilers. While current parallelizing compilers may succeed on small kernels, they often fail to extract any meaningful parallelism from whole applications. After a study of application codes, it was concluded that by adding a few new techniques to current compilers, automatic parallelization becomes feasible for a range of whole applications. The techniques needed are interprocedural analysis, scalar and array privatization, symbolic dependence analysis, and advanced induction and reduction recognition and elimination, along with run-time techniques to permit the parallelization of loops with unknown dependence relations.
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U2 - 10.1109/ICPPW.1996.538601
DO - 10.1109/ICPPW.1996.538601
M3 - Conference contribution
AN - SCOPUS:0000615819
T3 - Proceedings of the International Conference on Parallel Processing Workshops
SP - 149
EP - 161
BT - Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing, ICPPW 1996
A2 - Siegel, H.J.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1996 ICPP Workshop on Challenges for Parallel Processing, ICPPW 1996
Y2 - 12 August 1996 through 12 August 1996
ER -