Removing architectural bottlenecks to the scalability of speculative parallelization

Research output: Contribution to journalArticle

Abstract

Speculative thread-level parallelization is a promising way to speed up codes that compilers fail to parallelize. While several speculative parallelization schemes have been proposed for different machine sizes and types of codes, the results so far show that it is hard to deliver scalable speedups. Often, the problem is not true dependence violations, but sub-optimal architectural design. Consequently, we attempt to identify and eliminate major architectural bottlenecks that limit the scalability of speculative parallelization. The solutions that we propose are: low-complexity commit in constant time to eliminate the task commit bottleneck, a memory-based overflow area to eliminate stall due to speculative buffer overflow, and exploiting high-level access patterns to minimize speculation-induced traffic. To show that the resulting system is truly scalable, we perform simulations with up to 128 processors. With our optimizations, the speedups for 128 and 64 processors reach 63 and 48, respectively. The average speedup for 64 processors is 32, nearly four times higher than without our optimizations.

Original languageEnglish (US)
Pages (from-to)204-215
Number of pages12
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
DOIs
StatePublished - Jan 1 2001

ASJC Scopus subject areas

  • Hardware and Architecture

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