Remembrance of circuits past: Macromodeling by data mining in large analog design spaces

Hongzhou Liu, Amit Singhee, Rob A. Rutenbar, L. Richard Carley

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parameterized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental results show that we can automatically build useful nonlinear regression models for large analog design spaces.

Original languageEnglish (US)
Title of host publicationProceedings of the 39th Annual Design Automation Conference, DAC'02
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)1581134614
StatePublished - 2002
Externally publishedYes
Event39th Design Automation Conference - New Orleans, LA, United States
Duration: Jun 10 2002Jun 14 2002

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Conference39th Design Automation Conference
Country/TerritoryUnited States
CityNew Orleans, LA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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