Reliable low-power design in the presence of deep submicron noise

Naresh Shanbhag, K. Soumyanath, Samuel Martin

Research output: Contribution to journalConference article

Abstract

Scaling of feature sizes in semiconductor technology has been responsible for increasingly higher computational capacity of silicon. This has been the driver for the revolution in communications and computing. However, questions regarding the limits of scaling (and hence Moore's Law) have arisen in recent years due to the emergence of deep submicron noise. The tutorial describes noise in deep submicron CMOS and their impact on digital as well as analog circuits. In particular, noise-tolerance is proposed as an effective means for achieving energy and performance efficiency in the presence of DSM noise.

Original languageEnglish (US)
Pages (from-to)295-302
Number of pages8
JournalProceedings of the International Symposium on Low Power Electronics and Design
StatePublished - Dec 3 2000
EventProceedings of the 2000 Symposium on Low Power Electronics and Design ISLPED'00 - Portacino Coast, Italy
Duration: Jul 26 2000Jul 27 2000

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Digital circuits
Analog circuits
Semiconductor materials
Silicon
Communication

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Reliable low-power design in the presence of deep submicron noise. / Shanbhag, Naresh; Soumyanath, K.; Martin, Samuel.

In: Proceedings of the International Symposium on Low Power Electronics and Design, 03.12.2000, p. 295-302.

Research output: Contribution to journalConference article

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