Abstract
Scaling of feature sizes in semiconductor technology has been responsible for increasingly higher computational capacity of silicon. This has been the driver for the revolution in communications and computing. However, questions regarding the limits of scaling (and hence Moore's Law) have arisen in recent years due to the emergence of deep submicron noise. The tutorial describes noise in deep submicron CMOS and their impact on digital as well as analog circuits. In particular, noise-tolerance is proposed as an effective means for achieving energy and performance efficiency in the presence of DSM noise.
| Original language | English (US) |
|---|---|
| Pages | 295-302 |
| Number of pages | 8 |
| State | Published - Dec 11 2000 |
| Event | International Symposium on low Power Electronics and Design (ISLPED'2000) - Portacino Coast, Italy Duration: Jul 26 2000 → Jul 27 2000 |
Other
| Other | International Symposium on low Power Electronics and Design (ISLPED'2000) |
|---|---|
| City | Portacino Coast, Italy |
| Period | 7/26/00 → 7/27/00 |
ASJC Scopus subject areas
- Engineering(all)